1. Field of the Invention
The present invention relates to data processing apparatus, and in particular to data processing apparatus including memory cells accessed via bit lines.
2. Description of the Prior Art
It is known in the field of data processing systems to provide a memory, such as registers within a register bank, a cache memory or main memory, with bit lines running through the memory and via which data values are recovered from a chosen data storage cell within the memory. The bit lines within such memory are typically precharged during a precharge cycle to a given voltage and then selectively discharged by the chosen data storage cell in dependence upon whether the data storage cells is holding a "0" or a "1". A problem associated with bit lines is that they have a relatively large capacitance and so can take a comparatively long time to precharge and then selectively discharge. This can limit the cycle time of the system. In addition, when reading data values from data storage cells, it is important that they should be available and well defined by a certain point within the processing cycle. For these reasons, the length of time the bit line can spend bearing a signal value moving between those representing a well defined "0" or "1" is a problem.
In order to resolve some of these problems it is known to use tri-state output buffers at the outputs of a bit line such that the signal value on the bit line can be captured at a well defined time and variations of the signal value following the time at which the tri-state buffer can be prevented from influencing the output signal downstream of the tri-state buffer.
It is a constant aim within data processing systems to reduce the power consumption of the processors and the size of the circuits required. Low power consumption is highly desirable to extend battery life in portable systems and to allow faster operation without overheating.
FIGS. 1A, 1B, 2A and 2B of the accompanying drawings illustrate a tri-state output buffer 4. A bit line 2 connected to data storage cells (not shown) provides an input to the tri-state buffer 4. The tri-state buffer 4 is formed of a stack of four field effect transistors connected between the supply rail voltage and ground. The two transistors 6,8 nearest the supply voltage are p-type transistors. The two transistors 10,12 nearest the ground voltage are n-type transistors. Upstream of the tri-state buffer 4 is a storage element 14 formed of two inverters. the transistors 8,10 are supplied respectively when an enable signal that is low for the precharge phase of the clock cycle for the p-type transistors 8 and high for the n-type transistors 10. These two transistors 8,10 accordingly serve to isolate the signal on the bit line 2 from the storage element 14 during the precharge cycle. The transistors 6,12 serve as an inverter when the tri-state buffer 4 is not in its high impedance state to pass the bit line signal to the storage element 14.
FIG. 1A shows the tri-state buffer 4 in its transmissive state with the transistors 8,10 switched on. In this case a bit line signal value of "1" turns on the transistor 12 and turns off the transistor 6. Thus, a output signal value of "0" is passed to the input of the storage element 14. The output from the storage element 14 is inverted compared to its input and so the storage element output signal is a "1" that correctly reflects the bit line signal value.
FIG. 1B shows the tri-state buffer 4 in its transmissive condition with in this case a bit line signal value of "0". The transistors 8,10 are again switched on. The bit line signal value "0" in this case turns on the transistor 6 whilst the transistor 12 is switched off.
FIG. 2A shows the tri-state buffer 4 with the transistors 8,10 in this case switched off by the enable signals that indicate that the system is in the precharge phase of the clock cycle rather than in the read phase illustrated in FIGS. 1A and 1B. Thus, as the signal value of the bit line 2 changes from a "1" to a "0", this is not passed on to the storage element 14 which maintains its input and output values as shown in FIG. 2A.
Whilst the tri-state buffer 4 discussed above serves well in accurately capturing a bit line signal value and a known time and rendering the output immune to changes during the precharge phase, it suffers from the disadvantage of requiring two clock inputs to each tri-state buffer 4. In the context of a memory system, there are very many bit lines 2 being simultaneously read. Accordingly, the structures described above are repeated many times, for example in a register bank having 32-bit words and three read ports, this would result in 96 such tri-state buffers 4 being required. The physical space required for the six clock signal lines for these 96 tri-state buffers would require a significant circuit area. Furthermore, the need to drive the clock signal values on all of these clock lines and switch two transistors 8,10 within each tri-state buffer 4 consumes a disadvantageous amount of power.